This application claims the priority benefit of Taiwan application Ser. No. 90/118849, filed Aug. 2, 2001.
1. Field of the Invention
The invention relates in general to a test method and circuit for a non-volatile memory, and more particularly, to a test method and a test circuit for a non-volatile memory with a trapping layer.
2. Description of the Related Art
The gate structure of the non-volatile memory such as flash EEPROM has a control gate and a floating gate. The control gate is used to receive the operation voltage for controlling the memory cell, while the floating gate is used to store charges. With such a structure, as the floating gate is normally formed of a conductor such as polysilicon, the electrons injected for programming the memory cell distribute uniformly in the floating gate layer. The memory with such a floating gate structure can only function for one bit memory. Lately, memory with a dielectric layer to replace the floating gate has been proposed. Using the dielectric layer to trap electrons can cause a local distribution of the electrons. Two bits storage can be achieved to enhance the capacity of the memory cell.
FIG. 1 shows the structure of a non-volatile memory with a trapping layer capable of two bits storage. In FIG. 1, the ion implantation for forming the source 18 and drain 16 of the memory cell on a substrate is performed. A gate structure is on the substrate. The gate structure includes an oxide 10/nitride 12/oxide 14 structure. The nitride layer 12 is used as the trapping layer for electron capture. The techniques of channel hot electron injection and band-to-band hot hole injection are used for program and erase operations.
Since the trapping layer 12 is non-conductive, the electrons are localized at edges of the drain or the source of the memory cell while being trapped. That is, while applying the programming voltage to the gate and the drain, and a 0V to the source, a large electric field is generated between the gate and the drain edge. The electrons are trapped in the drain edge of the trapping layer 12 and localized therein. On the contrary, while applying the programming voltage to the gate and the source, and a 0V to the drain, a large electric field is generated between the gate and the source edge, and the electrons are trapped in the source edge of the trapping layer. Thereby, two bits storage can be achieved as shown as the locations of bit 1 and bit 2 in FIG. 1.
It is found that, after the program/erase cycle (P/E cycle) of the memory cell, the threshold voltage in the erase state increases with the increase of the retention time. The increase in threshold voltage causes the decrease of read current, and eventually causes the data stored in the memory cell to be invalid. For example, a threshold voltage must be below a specific value, a stage xe2x80x9c1xe2x80x9d can be distinguished as xe2x80x9c1xe2x80x9d. However, if the threshold voltage surpass the specific value, the stage xe2x80x9c1xe2x80x9d cannot be distinguished as xe2x80x9c1xe2x80x9d any more. That is, the data stored in the memory cell cannot be read correctly.
Therefore, to keep the memory working for a long time without failing after being produced, packaged, and held by the user, a test is required to ensure a normal operation even when the threshold voltage drifts. However, as the test time is limited, how to correctly and effectively predict the lifetime of the memory cell becomes a crucial task.
The invention uses the physical properties of the non-volatile memory with an insulating trapping layer to provide an effective test method and apparatus. The test method includes an accelerated test to estimate the lifetime of the memory cell within a short test time.
A reliability test method and apparatus are provided in the invention. An accelerated test is applied for a short test time, so as to determine whether a memory array can function normally within an estimated lifetime.
The reliability test method for a non-volatile memory includes the following steps. A relation curve of an applied gate voltage versus a read current degradation rate is determined. A read current degradation rate corresponding to an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding the actual gate voltage are obtained. With the applied accelerated test gate voltage, a test for a memory is performed continuously within the test time. Thereafter, each cell is read-out to judge whether the previously stored data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.
A quality test circuit for a non-volatile memory is also provided in the invention to test a memory array which comprises a plurality of memory cells arranged as a matrix of rows and columns. Each of the rows is coupled to a word line driver, and each of the columns is coupled to a bit line bias circuit. The quality test circuit of the non-volatile memory includes a word line bias generator coupled to the word line driver to input a word line voltage to perform the accelerated test.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.